1. Field of the Invention
The invention relates to a low voltage differential signal receiver, and more particularly to a receiver which has a constant voltage gain over a large input common mode voltage range.
2. Description of the Related Art
Because of the large common mode input range (0.2 v to 2.2 v) that a preamplifier for a Low Voltage Differential Signal (LVDS) receiver uses, the CMOS rail-to-rail input stages of the preamplifier comprise an NMOS differential pair connected in parallel with a PMOS differential pair. The NMOS input pair is able to reach the positive supply rail while the PMOS input pair is able to reach the negative supply rail. At the middle of the common mode voltage range, both the NMOS and PMOS input pairs are on, and the total transconductance gm has twice the gm of a single pair, assuming both pairs have the same gm value. Because of this, the total transconductance is not constant across the input common-mode range. This is an undesired phenomenon because it results in non-constant gain and variable unity gain bandwidth.
Below are the typical specifications of a Low Voltage Differential Signal (LVDS) receiver that the preamplifier needs to support:
LVDS Receiver Preamplifier Specifications:
Featuresfrequency 175 MHz to 945 MHzDC SpecificationsSymbolParametersConditionMinTypMaxUnitVTHDifferentialVOC = +1.2 V+100mVInput HighThresholdVTLDifferential−100mVInput LowThresholdVidInput differ-Rin = 100 ohm0.10.4Vential voltageIinInput currentVin = +2.4/0 V±10μAVcc = 3.6 VVocCommon Mode0.21.22.2VVoltage
All known prior art has attempted to solve the above mentioned problem of non-constant gm over the entire common mode input range. This is due to the application of the rail-to-rail input stage in Operational Amplifier design where large variation of gm impedes an optimal frequency compensation.
Referring now to FIG. 1, which was taken from the second reference listed below (W. Redman-White), we describe a typical circuit of the prior art. Rail-to-Rail input stages utilizing NMOS (M1, M2) and PMOS (M3, M4) differential pairs in parallel and joined by a Current Summation block, have three operating regions with respect to the Input common mode voltage range. When the common mode Input voltage is near the negative power supply (VSS), only the PMOS pair operates. For common mode Input voltages near the positive power supply (VDD), only the NMOS pair operates. For common mode Input voltages around mid-rail, both differential pairs operate and in this region, the transconductance of the input stage is twice as big as in the regions where only one pair (PMOS or NMOS) is on. The basic principle behind this is to vary the effective tail current in the active differential pair so that its gm doubles when the other is inactive. A simple way to achieve this is to use a transistor to sense that one of the pairs has lost current through a bypass transistor. Please refer to paper:                R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H. Huising, “A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries,” IEEE Journal of Solid State Circuits, Vol. 29, No. 12, pp. 1505-1513, December 1994, which describes a two-stage, compact, power-efficient 3V CMOS operational amplifier with rail-to-rail input and output ranges.        
An alternative technique is to increase the tail current bias on each side by a factor of 4 and to add additional devices inside each differential pair, which have a width 3 times that of the active devices. If the square-law operation is valid, gm will double, making up the deficit caused by the inactive pair, refer to below cited U.S. Pat. No. 5,208,552. In these implementations, the diverting transistor is 3 times wider than the driving transistor, which causes extra tail current added to the large signal limiting value. Hence slewing value doubles within the common input voltage range. To remedy this, a novel implementation that employs a diverting transistor of the same size as that of the driving transistor have been reported in                W. Redman-White, “A High Bandwidth Constant gm and Slew-Rate Rail-to-Rail CMOS Input Circuit and its Application to Analog Cells for Low Voltage VLSI Systems,” in IEEE Journal of Solid State Circuits, Vol. 32, No. 5, pp 701-712, May 1997, which describes a new rail-to-rail CMOS input architecture that allows circuit behavior which is nearly independent of the common mode level with respect to transconductance and slewing characteristics.        
Other approaches include:    a) controlling the sum total VGS−VT in the two pairs by current steering, and hence regulating the total gm, as referred to in            S. Sakurai and M. Ismail, “Robust Design of Rail-to-Rail CMOS Operational Amplifiers for a Low Power Supply Voltage,” IEEE Journal of Solid State Circuits, Vol. 31, No. 2, pp. 146-156, February 1996, which describes new bias circuits which provide currents to n- and p-channel differential pairs placed in parallel. The bias currents are a function of the input common mode voltage to allow the total transconductance of the differential pairs to be constant over the entire common mode range.            b) overlapping the transition regions of the tail currents for the NMOS and PMOS pairs to achieve constant overall transconductance gm, as referred to in            M. Wang, T. L. Mayhugh, S. H. K. Embabi, E. Sanchez-Sinencio, “Constant-gm Rail-to-Rail CMOS Op-Amp Input Stage with Overlapped Transition Regions,” IEEE Journal of Solid State Circuits, Vol. 34, No. 2, pp. 148-156, February 1999, which describes a design technique to maintain a constant gm input stage. The proposed technique overlaps the transition regions of the tail currents for the n- and p-pairs to achieve constant overall transconductance gm.        
U.S. patents that relate to the present invention disclosure are:    U.S. Pat. No. 4,555,673 (Huijsing et al.) discloses a differential amplifier containing a pair of differential portions and a summing circuit with rail-to-rail input capability and controlled transconductance. A current control regulates the operating currents for the differential portions.    U.S. Pat. No. 5,208,552 (Ryat) teaches the use of a rail-to-rail operational transconductance amplifier having a first operating range where the two differential amplifiers are active and second and third operating ranges where only one differential amplifier is active. Means are provided such that the transconductance of the active transistors in one of the second or third ranges is equal to twice the transconductance of the transistors in the first range.    U.S. Pat. No. 5,323,120 (Ryat) shows an Operational Transconductance Amplifier (OTA) with complimentary input transistor pairs where a dummy diode is provided for each pair. When the common mode input signal is near the positive or negative supply voltage, one of the pairs turns off. The diode loads act to increase the current through the other pair when this occurs. This results in a constant transconductance over the entire common mode input range.    U.S. Pat. No. 5,334,948 (Fong et al.) describes a CMOS constant operational amplifier which has two differential input circuits each having a current source and a compensation circuit. Each compensation circuit dynamically tracks the common mode input voltage relative to a respective supply voltage and generates a respective tracking voltage that is used to modulate the current source of the respective differential input circuit. The operational amplifier maintains virtually constant open loop gain throughout its entire operating range.    U.S. Pat. No. 5,371,474 (Wassenaar et al.) shows differential amplifier similar to U.S. Pat. No. 4,555,673 described above, but uses FETs and allows square-root current control.    U.S. Pat. No. 5,384,548 (Sakurai et al.) presents rail-to-rail operation by placing NMOS and PMOS transistors in parallel so that at least one type of transistors are operating in a high gain region throughout the entire input range. A constant transconductance bias means enables the rail-to-rail CMOS differential stage to possess a constant transconductance over the entire common mode voltage range.    U.S. Pat. No. 5,574,401 (Spitalny) discloses a CMOS amplifier input stage comprising NMOS and PMOS differential pairs connected in parallel. The tail currents of these differential pairs are controlled to maintain a nearly constant effective total transconductance, i.e., the combined transconductances of both pairs remain at least approximately constant as the input voltage swings through its operating range.    U.S. Pat. No. 5,631,607 (Huij sing et al.) teaches compact gm control circuits which makes constant the sum of the gate-source voltages of the complementary input transistors and thereby the gm of the input stage. The circuit implements a floating voltage source between the N and P-channel input stage transistors and the positive and negative voltage supply rails.    U.S. Pat. No. 5,646,575 (Sauer) describes a composite amplifier which is constructed by connecting the corresponding input terminals of a high-frequency amplifier and a precision amplifier together. Also the output of the precision amplifier is connected to the offset trim port of the high-frequency amplifier.    U.S. Pat. No. 6,384,683 (Lin) describes an intermediate stage for a rail-to-rail input/output CMOS operational amplifier. It includes a floating current source separating two current mirrors, where the ideal current source includes a floating current mirror enabling an output quiescent current to be provided which does not vary with changes in the voltage rails or the common-mode input voltage. This enables elimination of input offset caused by the mismatch of the two current sources.
Most of the above U.S. patents describe methods to achieve constant transconductance bias to enable the rail-to-rail CMOS differential stage to possess a constant transconductance over the entire common mode voltage range.
Related art techniques to provide constant gm bias for rail-to-rail input stage require extra current consumption; either through the use of current monitor/control circuits or by level shifting. In the LVDS receiver applications where the input stage has to work up to 945 MHz, current consumption of the input stage is very high and any current monitor/control would consume a considerable amount of current.
Besides that, having a constant gm at the input stage does not mean that the voltage gain will be constant. If this input stage drives a load Rout, then the voltage gain will be gm*Rout, which will vary by at least +/−10% if Rout is an integrated resistor.
In contrast, the present invention maintains a constant voltage gain over a large input common mode voltage range and at the same time is power efficient.